An Architecture and Prototype Implementation for TCP/IP Hardware Support

Today’s kernel based protocol implementation architectures may lead to a major performance limitation in the context of local high-speed networks. In this paper, we describe an approach for hardware support of transport layer protocols. Because of the high complexity of such protocols and various environmental conditions and requirements, such architecture must be very flexible and adaptable. Hence, we allow different configurations of the protocol engine, where specific protocol processing hardware, micro controllers or DSPs can be integrated. We outline a hardware/software partitioning, a heterogeneous protocol engine for protocol processing acceleration and describe its transparent integration into standard systems. In contrast to other approaches we reuse existing software implementations, significantly reducing the design complexity. The feasibility of this protocol engine is validated by utilising an intelligent network adapter board. For this implementation initial results are presented.